Last edit: 05-03-17 Graham Wideman

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High-speed SCSI text search engine.

1990: A defense contractor asked me to look into hardware text-search engines on behalf of a defense agency.  On studying certain commercial offerings, it seemed to me that what was needed was a hardware-based regular-expression state machine. As luck would have it Xilinx was starting to offer run-time programmable logic that looked like it might be perfectly suited to the job.

Thus was born the project to develop a proof-of-concept high-speed SCSI text search engine. The essential idea was a SCSI peripheral which could, autonomous of the host CPU, perform complex parallel text pattern searches either on the SCSI stream or, even more speedily, in onboard cache.

The bottom board contains a 680x0 CPU, AT&T DMA chip, dual SCSI controllers, ROMS and assorted glue to provide the basic SCSI behavior and handle communication with host system and slave drive(s).  The middle board is a "huge" RAM cache (how quickly "huge" becomes "tiny"!)

The topmost board provides a run-time programmable hardware state-machine for regular expressions. When a "hit" is detected, the address is FIFO-queued for "leisurely" reading by the CPU, and eventual retrieval of the surrounding text to the host. 

Configuring the Xilinx FPGAs on the fly required having our software understand how to compose FPGA configuration bitstreams, which despite a Xilinx NDA, was not available information. "Why would anybody want that info?" seemed to be  the question. This afforded us weeks of fun development time to analyze and pick apart the bitstream format. These days, "reconfigurable computing" is a hot field in its own right, and presumably developers are provided the bitstream format and tools to work on it. [Xilinx] [Giga]

Me: Architecture, search board and PAL design,  FPGA bitstream reverse-engineering, host search interface application, group coordination.
Bill Morris: 68K search and SCSI operating software
Jim Carver: CPU board design
William "Sonny" Son (founder of IGS): CPU and memory timing analysis and PAL revisions.

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